clock counter
英 [klɒk ˈkaʊntə(r)]
美 [klɑːk ˈkaʊntər]
时钟计数器
双语例句
- A wind-up clock ticked busily from the kitchen counter.
一只上了弦的钟在厨房的案子上嘀嗒响个不停。 - George looked at the clock on the wall behind the counter.
乔治瞄一眼挂在柜台后面墙上的那只钟。 - Real-time clock interrupt counter horological industry
实时时钟中断计数器钟表[计时器]工业 - Real-time clock interrupt counter
实时时钟中断计数器 - This paper analyses the packet pair bandwidth measurement algorithm, then discusses the requirement of it to clock precision and the schemes of clock selection in Windows system. Finally, it implements the algorithm by adopting thigh-resolution performance counter as the clock scheme.
分析了包对算法，讨论了包对算法对时钟精度的要求以及windows下包对算法的时钟选择方案，实现了采用高精度运行计数器计算时钟的包对算法。 - Phase-locked software accomplishes configuration for FPGA, chooses the input reference clock according to the priority of the reference clock source, and sets the enable port and step of counter.
锁相软件完成对FPGA的配置，根据参考时钟源优先级选择输入的参考时钟，设定计数使能和计数步长。 - The reference clock source is sent to FPGA in order to do sampling process. CPU adjusts the output clock frequency of OCXO dynamically according to the result of counter in FPGA.
参考时钟源送到FPGA中做采样处理，CPU根据FPGA中计数结果，动态调整OCXO输出时钟频率。 - To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。 - FPGA is divided into 6 function modules, and it completed clock generation, pixel counter, field signal generation, line counter and group, sync/ blank control signal generation, active test pictures generation respectively.
FPGA内部划分为六个功能模块，分别完成时钟产生、像素计数、场信号产生、行计数与分类、同步/消隐控制信号产生、有效测试图案产生。 - In its digital processing circuit, clock chip with high precision and temperature compensation is uesd as reference clock. High frequency reversible counter is used to count trimmed impulse signal forward or backward and two pathes SAW signals are selected timely by multichannel selector.
数字信号处理电路采用高精度、具有温度补偿的时钟芯片作为基准时钟，采用高频可逆计数器对整形后的脉冲信号进行正向或逆向计数，采用高性能的多路选择器控制两路SAW信号的定时选择。 - The paper introduces a method of digital electronic clock design based on EWB and the system is made up by silicon crystal oscillator, frequency divider, number counter, decoder circuit, LED display circuit, calibrated circuit, chirping circuit.
介绍了一种基于EWB软件设计电子钟的方法，系统由石英晶体振荡器、分频器、计数器、译码电路、LED显示电路、校时电路、整点报时电路组成。 - In the method, GPS is looked on as reference and the frequency difference between the Rb clock and GPS may be obtained indirectly, and the expensive high-resolution counter may not be needed.
该方法将GPS作为频率基准，间接得到了铷钟相对于与GPS的频差，避免了使用昂贵的高分辨计数器。 - A Real Time Clock/ Counter with Programmable Prescaler of Microcontroller
备有可编程预定标器的单片机实时时钟/计数器 - This paper present a design of digital clock with two alarms and introduce some circuits concretely such as three input circuit, reversible counter and output decoder/ driver.
简述了一种双闹钟数字时钟芯片的设计分析，具体介绍了其中三态输入电路、可逆计数器、输出解码/驱动器等电路的设计。 - A watchdog timer and its prescaler are also provided to improve the microcontroller anti-interference ability. A Real Time Clock/ Counter with Programmable Prescaler of Microcontroller
此外，通过备有监视计时器及其定标器可以有效地提高微机系统的抗干扰能力。备有可编程预定标器的单片机实时时钟/计数器 - To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。 - The clock network uses the global clock network replace the original counter, which strengthens the drive. Effectively eliminating the timing disorder, but also provide special hardware support for the characteristics of the algorithm.
采用全局时钟网络，代替原来的计数器时钟，增强了时钟的驱动能力，有效地消除了时序紊乱，还可以针对算法的特点提供特殊的硬件支持。 - To reduce the power, some low-power techniques are used in this design, such as system clock planning, system level power management, state optimization encoding, global clock gating, asynchronous counter, gate level power optimization, operands isolation, and so on.
为降低系统功耗，本文引入了多种低功耗技术，如系统时钟规划，系统级功耗管理，状态优化编码，全局钟控，异步计数器，门级功耗优化以及操作数隔离等等。